1. Field of the Invention
The present invention generally relates to the structure of cells of static memory devices and, more particularly, to a structure for cells of static memory devices which is substantially immune to so-called soft errors, generally caused by discharging of stored charge due to impact of energetic particles present in the environment.
2. Description of the Prior Art
Storage of data and instructions in a memory structure is necessary to virtually any data processor application. For this reason, among others, the development of high-performance memory structures has accompanied the development of data processing circuits and integrated microprocessors in particular. Thus, as integration density and processing power of microprocessors has increased, the same attributes have been sought in memory structures to obtain greater numbers of bits of storage per chip as well as to increase speed of the memory structure.
Memory structures are often considered to fall into one of two groups: dynamic memories and static memories. Dynamic memories offer the greatest potential for reduction of cell size and hence the potential for the greatest amount of storage per chip. Power consumption is also relatively low. On the other hand, the storage mechanism is almost entirely capacitive and, since some degree of leakage is unavoidable in any storage structure, the stored charge representing the stored data must be refreshed periodically. This requirement for periodic refreshing of stored data causes some periods during which the dynamic memory is not available to be read and thus increases the average cycle time and effectively reduces the speed of the response of the memory. Further, the mechanism for reading a dynamic memory essentially requires the use of the stored charge to cause a charge imbalance in a sense amplifier which establishes an appropriate logic voltage output for the memory. However, this operation also requires that the stored charge be rewritten to the cell, further increasing minimum read access time.
Highest memory read access speed is achieved by static random access memories (SRAMs). In such static memories, the data is stored in a bistable latch comprised of active circuits. Therefore no time is required for either refresh or other operations to restore charge after reading.
While SRAMs are not generally regarded as relying on stored charge (since, in normal operation, any charge lost through reading or leakage is continually replaced by operation of the active bistable circuit therein), when implemented with field effect transistors, voltages present on various nodes may cause storage of charge in a depletion region within or around a portion of the field effect transistors.
If an energetic particle from the environment, such as an alpha-particle, strikes an electrode surrounded by such a depletion region, electrons and holes will be generated within the underlying body of semiconductor material and will collect along the boundary of the depletion region. If the energetic particle strikes an electrode (e.g. an N-type transistor holding charge in a depletion region, the size of the depletion region and the voltage on the electrode will be reduced by the charge perturbation. Similarly, if an energetic particle strikes an electrode of a P-type transistor at low voltage, the charge perturbation will cause the voltage to be increased. Thus, if the charge perturbation is sufficiently large, the stored logic state may be reversed. This is commonly referred to as a "soft error" since the error is not due to a hardware defect and the cell will operate normally thereafter (although it may contain erroneous data until rewritten). Soft errors are increased by stand-by operation at reduced voltage.
Accordingly, a performance parameter of an SRAM storage cell is the critical charge, Qc, which is the amount of charge which will cause logic state reversal of the latch by causing a sufficiently large voltage disturbance. Unfortunately, both miniaturization and lowered operating voltages (migration to 3.3 V parts) of SRAM cells with higher integration densities and/or lowered operating voltages also reduce the value of Qc for stable operation of the cell. Accordingly, SRAMs have become increasingly vulnerable to soft errors. Accordingly, many attempts have been made to reduce this vulnerability to soft errors in recent years.
However, many of these efforts to reduce the incidence of soft errors often require additional electronic elements (such as additional transistors or even some refresh arrangement or redundant storage) which occupy additional space on the chip and reduce the potential degree of integration which is practical. Further, such additional elements often require further process steps or even additional layers to be formed in the semiconductor device, increasing cost and complexity and commonly reducing manufacturing yield. Accordingly, no particularly satisfactory solution to the problem of soft error reduction has heretofore been found.
Another feature of SRAMS which has recently become of interest is the provision of multiple ports for each cell. That is, the association of each cell with two or more independently operated bit lines. Such a feature allows effectively increased speed of access since a corresponding number of cells on an accessed word line could be read simultaneously or at least within the same memory cycle (since accessed addresses are a combination of the word line and bit line addresses). However, in known memory cell structures, the topology of the bit line access transistor in combination with the conductors forming the bit line and the connection to the bistable circuit are complicated since they have required additional insulator, semiconductor and conductor layers to be provided in the devices. Therefore, memories with more than two ports per cell are largely impractical and even the provision of a second port for each cell disproportionately increases cost and reduces manufacturing yield.